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Ordering number : ENN6628 LV1050M Bi-CMOS IC LV1050M Dolby Pro Logic Surround Decoder Overview The LV1050M is a Dolby Pro Logic surround effect signal-processing Bi-CMOS IC that in addition to LV1018 and LA2787 function, realizes virtual surround processing with the use of 5.1ch input signal. This IC can implement a Dolby Pro Logic surround system and various digital surround system in just one chip. * * * * * * * Functions and Features * * * * * * * * Pseudo-tap function. Built-in input switch for the L, C, R, LS, RS, and LFE channels. Virtual surround function (VDS 2 modes, VDD 1 mode). Simulated surround function for Dolby Digital. Input and output muting function. Reference level : 300 mVrms. Operating supply voltage : 8 to 10V. Package : QIP80E. * * Adaptive matrix. Center mode control (Normal/Phantom/Wide). 4ch/3ch logic control. Auto balance (ON/OFF). Prologic off-mode (Bypass/Full Bypass). On-chip memory (8k bit S-RAM). Variable delay time. Dolby surround mode : 15, 20, 25, or 30ms. Simulated surround mode : 7.5, 15, 20, 25, 30, 40 or 50ms. Modified B type noise-reduction. Center trim, surround trim (LS-ch, RS-ch) and LFE trim (0 to -31dB in -1dB steps). Input and output filter. Output : 7kHz L.P.F in dolby surround mode. 5kHz L.P.F in simulated surround mode. Built-in VDD. Simulated surround function. Fixed matrix : L+R, L--R. Front addition : 0, -2, -4 and -6 dB inverted and non inverted addition. Reverb function. Rear-channel monaural/stereo switching. Rear addition : 0, -2, -4 and -6 dB inverted and noninverted addition . Note : Dolby and Double D Symbol are registered trademarks of Dolby Laboratories Licensing Corporation. This IC is available only to licensees of Dolby Laboratories Licensing Corporation. San Francisco, C94103-4813, USA, from whom licensing and application information must be obtained. Package Dimensions unit : mm 3174-QIP80E [LV1050M] 0.8 1.0 0.8 0.35 23.2 20.0 1.6 * 41 64 65 0.8 0.15 40 * * 17.2 14.0 80 1.6 25 2.70 3.0max 0.8 1 24 * 0.8 21.6 SANYO : QIP80E Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 81000 RM IM No.6628-1/14 15.6 LV1050M Specifications Absolute Maximum Ratings at Ta = 25C Parameter Maximum supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VCC max Pd max Topr Tstg Conditions Ta 70C Twith board Ratings 10.5 1400 --20 to +70 --40 to +150 Unit V mW C C Note : TWhen mounted on a 114.3 mm ! 76.1 mm, t = 1.6 mm fiberglass epoxy printed circuit board. Operating Conditions at Ta = 25C Parameter Recommended supply voltage Operating supply voltage range Control input high level Control input low level Dolby level VO Dolby Symbol VCC VCCopg Conditions Ratings 9 8 to 10 3.5 to 5.5 0 to 1.5 300 Unit V V V V mVrms Electrical Characteristics at Ta = 25C, VCC = 9 V, f = 1 kHz, VIN = 300 mV (L, R inputs), VIN = 212 mV (C,S inputs), center and surround trim = 0 dB. Unless otherwise specified : in pro logic on mode and with the 400 Hz to 30 kHz bandpass filter used. Parameter Quiescent current Cch output level Output level deviation (Reference to the center output) Lch matrix rejection Cch matrix rejection Rch matrix rejection Sch matrix rejection Total harmonic distortion L, R, C Total harmonic distortion S S/N Lch S/N Cch S/N Rch S/N Sch Lch signal handling Cch signal handling Rch signal handling Sch signal handling Noise sequencer output Pro Logic off S/N (Full Bypass mode) Pro Logic off total harmonic distortion Symbol ICC VOC VOA Rj, L Rj, C Rj, R Rj, LS, RS THD THD S/N, L S/N, C S/N, R S/N, LS,RS SH, L SH, C SH, R SH, LS, RS VN S/N off L,R THD off L,R Dec1 Dec2 NR frequency characteristics Dec3 Dec4 Dec5 Virtual Dolby Surround S/N S/N v L, R 0dB, 1kHz, VCC = 8.5 V, f = 1 kHz, THD = 1% (L,C,R), THD = 3% (LS, RS) --20dB, 1kHz, VCC = 8.5 V, f = 1 kHz, THD = 1% (L,C,R), THD = 3% (LS, RS) 0dB, 5kHz, VCC = 8.5 V, f = 1 kHz, THD = 1% (L,C,R), THD = 3% (LS, RS) --20dB, 5kHz, VCC = 8.5 V, f = 1 kHz, THD = 1% (L,C,R), THD = 3% (LS, RS) --40dB, 5kHz, VCC = 8.5 V, f = 1 kHz, THD = 1% (L,C,R), THD = 3% (LS, RS) CCIR/ARM, Rg=10 k --1.5 --24.0 --1.5 --23.3 --46.8 55 VCC = 8.5 V, f = 1 kHz, THD = 1% (L,C,R), THD = 3% (LS, RS) CCIR/ARM, Rg = 10 k 65 65 65 60 15 15 15 15 50 80 Conditions Ratings min --2 --0.5 25 25 25 25 typ 120 0 0 35 35 35 35 0.02 0.1 76 77 76 72 16 18 16 16 70 90 0.007 0.0 --22.5 0.0 --21.8 --45.3 64 0.03 1.5 --21.0 1.5 --20.3 --43.8 90 0.05 0.7 max 135 2 0.5 Unit mA dB dB dB dB dB dB % % dB dB dB dB dB dB dB dB mV dB % dB dB dB dB dB dB No.6628-2/14 Block Diagram FC-L FC-R FC-LFE C-TRIM C-OUT FC-C LFE-OUT Lt DOLBY PROLOGIC ADAPTIVE MATRIX LV1050M Rt INPUT BALANCE CONTROL L-OUT R-OUT NOISE SEQUENCER FIXED MATRIX FRONT MIX/ VIRTUAL RS-TRIM AUDIO DELAY 7kHz L. P. F. B-NR REAR STEREO LS-TRIM RS-OUT LS-OUT FC-RS ILV00002 FC-LS No.6628-3/14 LV1050M Sample Application Circuit LL--LOW, LEAK 0.47 F R--BPF3 0.47 F L--R--RECT 0.15 F L+R--RECT 0.15 F 0.15 F 0.15 F 0.47 F L--RECT 0.47 F R--RECT 4.7 F DC OUT1 4.7 F DC OUT2 3.3 F 3.3 F 4.7 F 4.7 F DC OUT4 + + + + + + + + + + DC OUT3 L--BPF3 VCS--TH VLR--TH VCS--1 VCS--2 VLR--2 VLR--1 + 10 F + 10 F + 10 F + 10 F VRBF + 220 F VCC1 0.1 F MIX--OUT + + MIX--OUT 220 F A A 9 10 11 12 13 14 + 59PIN B 10 F 0.1 F R--BPF2 0.1 F 80 1 2 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 L--BPF2 0.1 F 0.1 F R--BPF1 L--BPF1 BPF S--DC--OUT RECT VCS RECT LOGDIFF PG PG LOGDIFF VLR RECT BPF 3 4 5 -+ 62 RECT FC--C--IN + 2.2 F FC--C--IN C--DC--OUT 61 R VCA VCA VCA VCA A B RT--IN + 2.2 F RT--IN R--DC--OUT 60 VOL R 50 K LT--IN + 2.2 F LT--IN L--DC--OUT 6 7 8 VREF 11PIN VCA VCA VCA VCA SW2 59 58 57 DC--CUT + 47 F A L S R C L VOL L 50 K C--MODE 0.47 F GND1 ANALOG SW1B CH--CONT BPL--CONT SW5 C B 3PIN S MODE + C--OUT 4PIN 5PIN 6PIN 56 C--MODE NOISE--FIL OSC SW4 A B NS--BPF1 22 nF C--OUT A B 10 F CTRIM D 55 54 53 NS--BPF2 47 nF OSC 680 pF CLK CLK VCC C A R NOISE--GEN DEV + AC--GND SW6 B 220 F SW5 A MIX--IN B L SW5 A B R S L L.P.F + 220 F 102 103 105 106 101 104 DELAY--IN DELAY--IN REVERB DATA--DEC B--NR A B 52 51 50 DATA DATA ENABLE ENABLE VSS SVC201 DIGITAL FILTER DELAY--OUT DELAY--OUT SW12 A A B B VOL/MUTE D GND C OUT--FILTER L--OUT L--OUT 10 F R--OUT + 15 16 17 C D L R--STEREO + A B C D A -R 20 K B C D + 8K--SRAM 20 K 49 48 47 CR--IN 0.1 F CR--OT 10 H LC--INE 51 pF 100 pF 15 pF R--OUT 10 F LS--OUT LS--OUT 10 F RS--OUT 20 K ADM--CONT 3 S SW11 A B A B C OSC + 18 19 20 21 20 K RS--OUT 10 F LFE--OUT 10 F ADM D 500 Hz HPF 36PIN 46 VDD A SW11 B LFE--OUT + LC--INB DC OUT + 0.33 F DC OUT--IN 45 44 VDD 0.1 F + A/D + + A SW11 B 220 F + + + 1 F 0.1 F VCC2 82000 pF + 22 23 24 43 A NS 3300 pF 220 F RS--DC OUT--OUT RS LFE--TRIM RS--TRIM LS LS--TRIM VIRTUAL VIRTUAL 42 41 D/A 82000 pF AGND ANALOG + 1 F RS--DC OUT--IN 25 LS--DC OUT--OUT 26 27 LS--DC OUT--IN PYSRDIN POAPR 28 PYSLDIN 29 POAPL 30 31 FC--LFE--IN 32 FC--RS--IN FC--LS--IN 33 FC--R--IN 34 FC--L--IN 35 VIR--OFP 36 0.022 F 7KL.P.F 37 NR--C2 38 DET 39 IREF 40 100 pF 200 pF FC--LFE--IN 2.2 F FC--RS--IN 2.2 F 2.2 F 2.2 F + 1 F + 0.1 F 0.1 F + + + + FC--LS--IN FC--R--IN FC--L--IN 2.2 F 39 k + + 2.2 F ILV00007 Notes on LV1050M Usage * Power is supplied to the matrix and steering control circuit in the LV1050M Dolby Prologic surround decoder from VCC1 (pin8) and GND1 (pin57). Power is supplied to the delay line circuit in the surround block from VCC2 (pin22)and GND2 (pin41), and power is supplied to the digital circuit blocks from VDD (pin45) and VSS (pin50). * One Point that requires care is that mutual interactions (due to, for example, common impedances) between these power supply lines may influences the signals being processed, if this happens, phenomena such as souns not being moved smoothly may occur. * To prevent such phenomena from occurring, observe the following recommendations. - Design the printed circuit board layout so that all VCC and ground lines are as short and as wide as possible. - Connect all VCC and ground lines to the power supply independently. - Connect capacitors (about 220F) between each of the VCC and ground pairs as close to the IC pins as possible. Note : A sample power supply line layout is presented in the above diagram for reference. No.6628-4/14 47 pF + C C B B C C C C B A D B B B B A A D A A A D D D D R L |
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